(1) Field of the Invention
The present invention relates to a frequency synthesizer having a phase-locked loop (PLL). The frequency synthesizer will be abbreviated to a PLL synthesizer hereinafter.
(2) Description of the Prior Art
As will later be described with reference to FIG. 1 of the accompanying drawings, a conventional PLL synthesizer comprises a voltage controlled oscillator (VCO). The oscillating frequency of the VCO is divided at a variable frequency divider and the resultant divided signal is compared in frequency and phase with a reference signal. The compared output is fed back to the VCO as a control voltage signal. The oscillating frequency of the VCO is controlled by the control voltage signal. When a division factor of the variable frequency divider is changed, the oscillating frequency of the VCO changes in steps of a frequency of the reference signal which is referred to as a step frequency. Thus, a desired frequency signal is obtained, as an output signal of the PLL synthesizer, from the VCO by adjusting the division factor of the variable frequency divider. In practice, a reference signal having the step frequency is obtained from a reference signal generator through a fixed frequency divider.
In the known PLL synthesizer, the phase noise characteristic of the VCO is degraded and it is difficult to determine the step frequency to be a reduced value, as will later be described.